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IBM 000-923 : Netcool/Precision IP V3.6 Exam

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Exam Name : Netcool/Precision IP V3.6
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IBM V3.6 techniques

establishing a Reusable IP Platform inside a equipment-on-Chip Design Framework focused in opposition t an tutorial R&D ambiance | 000-923 Study Guide and Test Prep

by way of Brendan Mullane and Ciaran MacNamee,Circuits and device analysis Centre (CSRC),tuition of Limerick, Limerick, ireland

abstract:

A key problem dealing with the semiconductor business is to mix highbrow Property (IP) from a number of sources without delay and effectively. Design times are continually pressurized through time to market necessities and lengthening complexity. Industrial practices for setting up equipment-on-Chip (SoC) IP have developed under these pressures, but applying these practices in an tutorial atmosphere gifts further challenges. The thought for setting up a framework for generating IP was in line with this reuse revolution and the merits it brings to R&D. The potential to design high great IP and to enable work practices for reuse methodology helps to achieve working SoCs in a timely and productive manner. This paper describes a methodology for imposing IP reuse practices appropriate to an educational atmosphere.

1. Introduction

a lot of factors are mandatory for productive IP use, flexibility of integration, more suitable ease-of-use, minimized charge, and respectable work practices for constructing IP. This paper is in accordance with genuine work setting up an ASIC the usage of 0.35ìm technique know-how. The structure during this IC is akin to SoC designs that use an 8-bit CPU and linked peripherals. it is shown that the framework for IP construction based all over this challenge can be certain a hit deployment of each current and new designs in future tasks.

The latest vogue in SoC design is to utilize existing IP as a whole lot as viable. IP within the form of CPUs, DSPs and controllers, are being reused in new IC tasks at semiconductor techniques design residences. Engineering teams now design chips with thousands and thousands of gates in lower than a yr. just recently, such productiveness would had been unimaginable, even unthinkable with out hardware IP reuse. Most academic environments won't have the materials and infrastructure to allow such engineering capacity, despite the fact the underlying principles of reuse will also be applied to permit more beneficial IP generation and skills retention for effective R&D.

This paper introduces a set of instructions and a methodology used to be sure a constant approach to designing IP and to allow for reuse of these modules in future tasks. the primary stage turned into to examine premiere industrial practice. Work describing the ASIC building cycle and its impact on IP generation changed into conducted. a collection of specifications for making certain IP satisfactory and ease of integration turned into additionally organized. A key aim was to be sure competencies may be retained in the tuition centre to bear in mind anticipated graduate turnover.

2. IP Reuse Framework in CSRC

A evaluation of the regular considerations in design use and reuse changed into initiated [1]. a considerable number of IP standards were reviewed and these protected Freescale’s Semiconductor Reuse standard [2], VSI Alliance’s set of specifications for constructing SoCs [3] and OpenMORE [4]. IP reuse may certainly not have happened with out requirements or devoid of the underlying infrastructure [5]. Design and verification reuse, a truth of life nowadays for many SoC designs, ensures the productiveness gap is saved manageable[6]. Design reuse regarded an easy concept that can also be with no trouble adopted, has persisted to be frustrating in observe. complications exist in getting engineers to trust that reusable IP will work every time it's used in an IC. featuring IP support capabilities and adoption of a proper verification manner develops this have faith.

2.1 SoC architecture and Infrastructure

The purpose of this project turned into to establish a design methodology for producing IP. The methodology worried architectural selections and choice of design-flows for IP construction accompanied through the prerequisite IC design equipment. challenge standards such because the SoC architecture, third-birthday party core use, in-condo IP construction and the system bus interface were all regarded before the IC architecture changed into concluded and the peripheral integration became performed. The basic SoC architectural diagram is proven in figure 1 and the comprehensive chip was taken via verification and the lower back-end levels of synthesis, design, static timing analysis and closing design rule checking.

figure 1: SoC Design structure

the following key choices have been made when it comes to the IP aid structure.

2.1.1 Peripheral Bus Interface

The option of a common SoC device bus for connecting the CPU to the system peripherals become critical to the pursuits of this challenge. the use of a standardized bus structure is simple to setting up reusable IP. a lot of bus necessities were investigated for the needs of the CSRC IC tasks. The 8051 CPU become used in this design and however the interior particular feature Register (SFR) bus was considered, the authors wished to employ a common bus design to be reused in different IC implementations.

lots of the foremost IC and IP companies base their IP portfolio development round a single SoC bus structure. Semiconductor companies corresponding to ARM and LSI good judgment use the open supply AMBATM [7] bus general. IBM makes use of its personal proprietary CoreConnectTM [8] bus average. The OpenCores initiative uses the WishboneTM [9] described bus interface. The authors accompanied that the AMBA bus architecture changed into well supported amongst the IP dealer community. This huge acceptance arises from the availability of an open bus common it truly is license free and smartly proven in latest SoC designs. clients have a high diploma of self belief making a choice on IP this is considered seller independent. moreover, the AMBA bus is neatly supported by EDA agencies offering verification guide. The AMBA bus was chosen because the bus interface for CSRC SoC tasks for these explanations.

The AMBA bus enables partitioning for modular designs[10]. Its methodology for embedded processor design encourages both a modular and first time appropriate gadget design. It additionally hastens product migration by using aiding module reuse. In particular, the AMBA APB bus specifies a versatile interface and small overhead assist for low bandwidth peripherals. The IP design the use of the AMBA interface is made simpler through partitioning the excessive-conclusion and low-end devices in the equipment and helps power efficient designs. all of the peripherals during this design used the AMBA - superior Peripheral Bus (APB) as the standardized interface. The CPU as a single bus grasp become interfaced to all the peripherals by the use of an in-house designed AMBA bridge interface.

The advantages of the usage of a common bus interface for core building are smartly documented [1, 10, 11]. A pattern AMBA APB register module, shown in figure 2, became advantageous for demonstrating the favored interface design to postgraduates. The RTL code for this module helped the team to take into account the concepts of decent coding practice to include parameterization and Tested the use of revision control for code changes and computer virus fixes. the entire IP developed in this IC challenge can also be reused in every other AMBA based SoC purposes and this aids future product and platform development

determine 2: pattern APB module

2.1.2 third party Core Licensing

a different tremendous task changed into to designate an appropriate microcontroller for the challenge. The IP group turned into approached with regard to licensing of the CPU and debug cores. there were a couple of features to licensing IP cores from an educational standpoint. It became essential to make certain a licensing association turned into made using a non-industrial analysis- licensing mannequin. Many providers were handiest organized to license their cores according to a full industrial association and the costs quoted were past an academic research price range. Some vendors have been willing to agree with a reduced non-business license price with the re-introduction of full fees offered the IC proceeds to commercial software. other IP vendors confined their set of deliverables to FPGA netlist implementation handiest. This confined our choice of third celebration CPU and debug cores. happily, some IP businesses had adventure dealing with academic cases and had been organized to liberate IP deliverables and help for non-industrial analysis pastime at a decreased can charge. The leading writer changed into able to carry out a survey of suitable cores and got here to an contract for the 3rd party IP mandatory for the SoC assignment.

2.1.3 Design Flows

The ASIC design movement and digital Design Automation (EDA) tool selection is a vital element of an effective IP framework. The option of equipment ought to complement the design flows and assist reusability of IP. The centre accesses tool units provided as educational programmes from the semiconductor EDA companies. The CSRC also has entry to customary EDA tools by the use of the Europractice[12] utility carrier scheme. Our FPGA and Digital design flows were drawn up around the availability of those tools and to plan the SoC IP construction and integration. These flows have been beneficial in identifying the distinct ranges involved in the development of IP and SoC designs. besides the digital design stream, a circulate for FPGA prototyping became also added. The FPGA building makes it possible for for an inexpensive design validation platform and adds self belief by way of guaranteeing relevant conduct before ultimate tape-out.

2.1.3.1 Digital IC Design circulate

The digital design follows the classic ASIC implementation route. a couple of semiconductor company web sites and technical paper searches printed the standard design circulation that exists for digital ASIC design [13], [14].

determine three: Digital IC design move

The design circulate and tools alternative as drawn up in determine 3 have been tailored to device availability and the choice of IC techniques offered by way of Europractice.

2.1.three.2 FPGA Design stream

The FPGA stream in determine 4 is very akin to the digital IC design stream, however the design tools to enforce and application a FPGA design are different. The assignment used the Xilinx design kits and equipment made accessible by means of the Xilinx tuition Programme. We used Xilinx Spartan 2 and three boards to put into effect the digital design elements. The Xilinx ISE webpack is a set of tools that takes Verilog RTL code and runs it via synthesis, physical layout to machine configuration. The last bit file can then be downloaded to application the FPGA device to determine the useful conduct of the digital design. FPGA verification recommendations and their magnitude in design validation and reuse are discussed later.

figure four: FPGA Design circulate

2.2 CAD Infrastructure

The CAD infrastructure became more suitable to carry out SoC building in the centre. The original constitution included three low-grade UNIX servers for running the IC design tools and keeping mission facts. A plan turned into initiated to Excellerate the IT hardware wants. every of the user PCs had been installed with VMware Linux, enabling clients to preserve their home windows OS however more importantly every computer might use its personal CPU processing energy with Linux to bring enhanced performance. Two high power Linux mainframes, got for keeping the task databases were additionally utilized as license servers for the supported EDA equipment. the brand new set-up offers the performance necessities to perform IC R&D inside the CSRC centre.

a further step was identifying the EDA equipment necessary for IP construction. equipment for verification and making certain best of RTL code have been now not in region. despite the fact the use of our Europractice membership, the centre had access to primary EDA equipment at a reduced charge. equipment akin to ModelSim for RTL verification and Leda for RTL analysis have been got. The latest edition of Design Compiler became also upgraded in line with business necessities.

three. Design Methodology and IP reuse Implementation

utility of reuse pays off in terms of building charge and time-to-market. This part summarizes the building milestones for a regular IP design. Defining the circulate and associated design studies helps guarantee a repeatable, high satisfactory, and reusable block of peripheral IP. a further improvement of a documented move is that different design companies can use this technique to enhance IP in an identical method; ensuring IP is consistent in its implementation, integration movement, deliverables, and ordinary great.

three.1 building Milestones

IP/SoC design milestones are essential to the start of working silicon and achieving a ‘correct first time’ policy. These milestones are markers positioned down throughout the development part to manipulate and measure the design endeavor and growth. These markers indicate studies taking place all the way through the important tiers of the design phase from delivery to conclusion. Milestones take location on the herbal progression of the task. figure 5 and table 1 describe the signal-off milestones to include all fundamental design stories.

determine 5: IP construction Milestones

desk 1: IP construction levels

stageReview Description FSR practical Spec evaluate purposeful specification is finished, details on effort estimation, work breakdown constitution and time table. DSR Design start evaluation Design delivery, working towards, RTL coding & synthesis checklistTPR verify Plan evaluate comprehensive specification of verification atmosphere, examine cases, bus-fashions, transactors. RCR RTL Code review RTL bug fixes recognized through exhaustive verification & RTL Lint/code checking TLR Trial layout evaluation establish floorplan and operate P&R. Floorplan in keeping with module connectivity, resolve congestion and timing –examine clocking FVR closing Verification assessment high priority checking out achieved. generic bugs within the RTL are fastened. coverage analyzed. Low precedence testing adequate. FDR last Design review review integrity exams (DRC, LVS) STA, test Vectors and ultimate gate-level verification with finished layout timing.

3.2 venture Database structure

A standardized listing constitution is vital for IP reusability. a good and simple to use database constitution ensures compatibility and consistency of peripheral design. IP building includes specification, coding and verification as key design tiers. subsequently, many help file formats are required. IP renovation is additionally a key thought in IP reuse. The potential to log and hold tune of design adjustments is a must have to the typical quality of the design. figure 6 shows the CSRC directory constitution to guide the IP development degrees.

determine 6: usual CSRC directory Database

3.3. Reuse instructions

3.3.1 Specification studies

The design stories are enormous in terms of producing a framework for IP building and reuse. These experiences help documentation and make sure decent design practices.

3.three.2 useful Specification

This doc gives a detailed purposeful description of the module and is written just before the IP construction. The FSR evaluation takes vicinity to be sure all features of the peripheral performance are coated. The specification may be used to beginning the design and RTL coding. The purposeful specification has to be up to date hence with any additional facets necessities. The CSRC uses a draft template document as a guideline for producing practical block and IC design specifications.

three.3.three RTL Coding and evaluation

RTL construction contains coding the peripheral in a hardware description language similar to Verilog or VHDL. Verilog RTL changed into used and a collection of coding guidelines for the IP technology was issued. This set of coding concepts ensures consistency, coding trend pleasant and offers for greater protection. The RCR is a high degree overview of the RTL code to be certain it's stylistically correct and maintainable. The intent is to double-assess the code first-class. The foundation for this review is the RCR checklist. RTL evaluation is performed the use of Leda for crosschecking RTL code rules against the Reuse Methodology manual (RMM). preliminary FPGA/IC synthesis can also be used to spotlight any RTL issues with regard to synthesis.

three.3.4 Revision manage

Revision handle is fundamental to the conception of design reuse and ensures important guidance isn't misplaced all through the design section. Revision control and file administration is notably important right through RTL coding as any code misplaced all over this stage can significantly affect the ordinary design timeline. To assist manipulate info, engineers use source manage management systems. These are usually bundled with the Linux operating techniques or attainable from GNU (RCS, CVS, Subversion). These code management systems provide an entire heritage of each file as separate versions.

three.three.5 worm protection

dealing with bugs is a vital consideration for any design framework. it is average to discover purposeful irregularities in the design and their occurrence does not replicate the talents of hardware designers. once an issue is identified, it needs to be resolved. All design groups want a way for tracking concerns and ensuring their decision. The authors proposed conserving a malicious program record for any design linked concerns.

3.four Verification and Validation ambiance

The verification section is vital to offering first time working silicon. Our verification methodology makes use of a twin song strategy. Verification occurs on the module stage and also on the SoC device stage. The Module Verification environment (MVE) functionally validates the core and ensures all design traits were comprehensively confirmed. The SoC Verification ambiance (SVE) assessments the cores’ conduct on the system degree and in selected exams the connectivity between the core interfaces. An FPGA/ASIC design verification approach was used to validate the project at the system SoC level.

three.4.1 Module Verification ambiance (MVE)

a necessary a part of the MVE become the generation of the APB Bus practical model (BFM) to generate the purposeful habits of the system bus. all of the peripherals have been based on this standardized bus structure and this enabled using a conventional mannequin to check the bus interface and registers contained in the peripherals. This mannequin further provided a simple to make use of verify environment. The diagram in figure 7 illustrates this. The BFM utilized Verilog tasks for examine/write accesses, including wait state control and changed into reused in all the peripheral look at various environments. The BFM became advantageous for operating tests to achieve confidence in the practical habits and for concentrated on excessive code coverage.

figure 7: APB Bus practical model

three.four.2 SoC Verification environment (SVE)

The SVE consisted of a separate however similar look at various solution for FPGA prototyping and the ASIC system degree verification. The FPGA solution changed into positive for mapping the comprehensive SoC RTL code to encompass the CPU, debugger and all the peripherals onto a FPGA. figure 8 illustrates the fundamental structure carried out onto the FPGA gadget.

figure 8: FPGA Prototype Validation

The CPU and different leading peripherals are related collectively as a single platform and checks have been developed in R8051 CPU core software code to operate the peripheral exams. The ASIC verification ambiance is corresponding to the FPGA verify mattress, apart from during this case all tests had been run using RTL and manner particular gate-level stimulations. every of the peripheral firmware checks developed for the FPGA prototyping have been reused at ASIC equipment degree.

4. results and Conclusions

The mission purpose became to put in force a SoC design framework for the birth of reusable IP. The chosen standard device bus aided the building of plug and play peripherals that can be reused in many other SoC functions. The building of the 8051 CPU exterior records bus to gadget bus-bridge offered for a standardized interface and simplified the peripheral development.

The design flows of Figures 4 and 5 have been followed to be sure a consistent design approach for the building and equivalent help for business regular EDA tools. The directory constitution as explained in section 3.2 become also essential for associating info with every stage of the IC construction and protecting a smartly-managed database. each of the applied IP blocks follows this standard database constitution and this ensures reusability going ahead. Design reviews ensured confidence and quality of the IP block design. The Verilog code changed into reviewed to be certain revision handle and RTL coding instructions were adhered to. an analogous review turned into conducted to make certain the verification environments at module and system stage had been applicable to verify the functionality of those designs. The RTL changed into validated on a FPGA device and exams had been conducted on the gadget level to verify the peripherals linked to the 8051 CPU.

The IP framework as mentioned during this paper is relevant for implementation in an academic centre wishing to carry out a reusable IP programme. this methodology and reuse options are popular in industry, however because of funding and aid constraints, might also now not all the time be convenient to install in an tutorial ambiance. This paper discusses the implementation of IP construction for decrease bandwidth peripherals; having said that the underlying concepts of IP use and reuse are the same.

four.1 educational Centre Specifics

body of workers requirements for research are ultimately resourced from graduates pursing MEng and PhD degrees. within the CSRC, workforce and educational researchers are answerable for main tasks and mentoring students. The graduates need knowledge development to deliver them up to speed and having a structured construction methodology makes it possible for deliverables to be met in a well timed trend. The merits of IP potential retention turned into another reason for introducing the IP building framework, as work generated on tasks carried out in the past would have been problematic to growth as soon as postgraduates had completed their research levels. This turned into an important challenge to resolve, as useful venture work conducted during the past might also had been unnecessarily lost.

four.2. Future thoughts

The cores can be additional enhanced with the aid of providing a gadget C or C model as a part of the developmental tiers to extra the degree of abstraction and to velocity up design verification and application development.

SystemVerilog is a hardware design and verification language with superior features meant to assist users boost reusable, transaction-degree, insurance-pushed testbenches. concepts reminiscent of fact based mostly Verification (ABV) may be utilized to the bus protocol to display screen pin recreation and the application of coverage-pushed exams add self belief in working silicon and provide an exhaustive testing ambiance. These aspects introduce ideas of verification reuse.

Design for verify (DfT) is commonly excluded from the design circulation in an educational atmosphere. DfT is a really essential feature vital for IP reuse. The IEEE 1500 typical for Embedded Core examine (SECT) specifies a core wrapper design to accommodate DfT facets. This IEEE 1500 compliant wrapper design might supply a valuable extension to the present IP building stages.

5. Acknowledgements

The authors acknowledge the assist of the Circuits and methods analysis Centre (CSRC) in the digital and computer Engineering (ECE) Dept. on the college of Limerick.

6. References

[1] Australian Microelectronics network, "IP design and Re-use," Jun, 2005.

[2] Freescale Semiconductor, "Semiconductor Reuse common v3.2," Feb, 2005.

[3] VSIA Alliance, "VSIA structure document v1.0," Mar, 1997.

[4] P. Bricard, Jean-Pierre Gukguen, "applying the OpenMORE assessment software for IP Cores," in ISQED 2000: Synopsys, Mentor graphics, March, 2000.

[5] J. Shandle, G. Martin, "Making embedded application reusable for SoCs," EETimes, Jan, 2002.

[6] J. Bergeron, "Writing Testbenches - practical Verificaton of HDL fashions", Kluwer educational Publishers, 2003.

[7] ARM, "AMBA™ Specification (Rev 2.0)," ARM LTD, may 1999.

[8] IBM. CoreConnect Bus. structure, "http://www-03.ibm.com/chips/products/coreconnect/."

[9] R. Herveille, "WISHBONE device-on-Chip (SoC) Interconnection architecture for transportable IP Cores," OpenCores firm, Sep, 2002.

[10] D. Flynn, "AMBA: Enabling Reusable On-Chip Designs," IEEE Micro, vol. 17, 1997.

[11] M. Kaskowitz, "bendy, requirements-based IP key," EETimes, Dec, 2002.

[12] Europractice, "http://www.msc.rl.ac.uk/europractice,"

[13] QualCore logic, "QualCore SoC flow."

[14] V. P. Nelson, "VLSI/FPGA Design and examine CAD tool circulation in Mentor pics," Feb 15, 2006.

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